This invention relates in general to techniques for simulating integrated circuits and, more particularly, to such techniques which include determining various capacitances associated with circuit devices within an integrated circuit.
An integrated circuit typically includes a number of circuit devices such as transistors, as well as interconnections between those circuit devices. The interconnections between circuit devices typically include parasitic capacitances, which can affect the operation of the integrated circuit. For example, in a conductive path which connects one transistor to another transistor, a parasitic capacitance associated with the path may have the effect of creating propagation delays that delay signals traveling along the path.
In older semiconductor technologies, where a given integrated circuit would have a larger size than it does in current semiconductor technologies, conductive paths that connected respective circuit devices were somewhat longer than in current technologies, and had greater spacing between them. In current technologies, conductive paths that connect devices are narrower in width and are closer to each other than was the case in prior technologies. As a result, and due to the decreasing size of the devices themselves, the parasitic capacitances associated with interconnections between circuit devices have come to represent a greater percent of the cause of overall propagation delays than was the case for past technologies. This is particularly true for static random access memory cells (SRAM cells), which have a complex physical structure, and for which speed is a critical operational characteristic of interest.
A further consideration is that, as integrated circuits become progressively more complex due to increasing levels of integration, the time and effort involved in designing new integrated circuits cannot be permitted to progressively increase at a rate proportional to the increasing complexity of the integrated circuits. Integrated circuit design tends to be somewhat iterative, in that a design is prepared, then evaluated, then modified, then evaluated again, then modified again, and so forth. Consequently, new design techniques are needed which facilitate rapid and accurate evaluation of how a particular design will perform. Accuracy is as significant as speed, because accuracy can reduce the number of iterations in the design cycle.
In the early days of integrated circuits, in order to evaluate whether a given integrated circuit would operate in a satisfactory manner, it was often feasible to build and test an actual prototype of the integrated circuit. Since then, however, as integrated circuits have become progressively more complex, progressively greater emphasis has been placed on techniques for effecting theoretical simulations of the operation of an integrated circuit and the devices in it, for example through the use of computer programs.
With respect to specific circuit devices, such as transistors, computer models have been developed that provide a relatively accurate representation of the device itself, including capacitances which are internal to the device. These internal capacitances are commonly referred to as device capacitances. On the other hand, with respect to capacitances external to the device, including capacitances between structure internal to the device and structure external to the device, existing computer program tools do not accurately take into account these additional capacitances, which are common referred to as interconnect capacitances. As discussed above, the effect of interconnect capacitances is becoming a progressively more significant factor in the cause of propagation delays, as the level of integration progressively increases. Accordingly, there is a progressively increasing need for simulation and modeling techniques that will take into account all relevant capacitances associated with devices in an integrated circuit, including both device capacitances and interconnect capacitances.
As mentioned above, there are existing computer programs which take device capacitances into account, but not interconnect capacitances. In order to also take interconnect capacitances into account, special provisions are needed, and the following is one current approach used in the art. A layout for all or part of an integrated circuit is supplied to a computer program which is a circuit description file generator program, and which produces a circuit description file that is a representation of the integrated circuit, or a selected part of it. The circuit description file can be supplied to an existing simulator program, in response to which the simulator program can simulate the operation of the integrated circuit.
The circuit description file includes a definition of each circuit device such as a transistor, and an accurate definition of device capacitances that are internal to each such device. However, existing circuit description file generator programs do not take into account certain other types of capacitances, such as the interconnect capacitances which are becoming progressively more critical factors in the design and evaluation of integrated circuits. In order to compensate for this, the layout for all or part of the integrated circuit is supplied not only to the circuit description file generator program, but also to a special extractor computer program, which is capable of identifying capacitances other than the device capacitances. The extractor program also receives a technology definition. The output of the extractor program is a capacitance definition, which is also sometimes referred to as a capacitance matrix.
Since the above-mentioned circuit description file generated for the simulator program already includes an accurate representation of the device capacitances within each device, there would be duplication if these device capacitances were left in the capacitance definition. Therefore, an attempt is made to remove them, so as to leave other capacitances that are not taken into account by the input file, such as interconnect capacitances. However, the device capacitances are not always clearly separate from the interconnect capacitances in the capacitance definition, as a result of which some approximations have to be made in an attempt to remove the effects of the device capacitances, and these approximations introduce errors that limit the accuracy of the final result.
The circuit description file and the interconnect capacitances, to the extent that the interconnect capacitances can be separated from the device capacitances, are both subsequently supplied to the simulator program, usually after being merged into a single file that is typically referred to as a circuit description with parasitic capacitances. The simulator program then uses this information to simulate the operation of the integrated circuit, in a manner which is more accurate than would be the case if the simulator program received only the circuit description file, without any definition of the interconnect capacitances. While this known approach has been generally adequate for its intended purposes, it has not been satisfactory in all respects.
More specifically, with respect to the extractor computer programs discussed above, one common class of existing programs take a somewhat two-dimensional approach to the analysis of information derived from the layout and the technology definition. Programs in this class tend to find most interconnect capacitances, but the values which they determine for these capacitances frequently include a substantial degree of error. This is sometimes due in part to the need to make approximations of the type discussed above, in an attempt to separate the effects of interconnect capacitances from the effects of device capacitances. Consequently, it is common for programs in this class to identify capacitance values which have an average degree of error of about 50%. In other words, the values determined by these programs for interconnect capacitances may, on average, be 50% higher or lower than the actual values. As discussed above, interconnect capacitances are becoming progressively more significant as a factor in the analysis of integrated circuits. Consequently, the 50% error level is becoming progressively less acceptable to circuit designers.
A more sophisticated class of extractor programs takes a somewhat three-dimensional approach to the analysis of the information derived from the layout and the technology definition. Extractor programs in this class provide a greater level of accuracy than the other class of extractor programs discussed above, but still suffer from problems of the type discussed above, such as the need to make approximations in an attempt to separate the effects of interconnect capacitances from the effects of device capacitances. Consequently, these extractor programs determine values for interconnect capacitances which have an average degree of error of about 16%. This is effectively the highest level of accuracy available in the existing art. Nevertheless, as the level of integration progressively increases and interconnect capacitances become a progressively more significant factor in the simulation and analysis of integrated circuit designs, integrated circuit designers are looking for an even greater level of accuracy in the identification of values for interconnect capacitances.
From the foregoing, it may be appreciated that a need has arisen for a method and apparatus for facilitating simulation of an integrated circuit in a manner which ensures that all significant capacitances within the integrated circuit are accurately identified and taken into account for purposes of the simulation.
According to the present invention, a method and apparatus are provided to address this need, and involve simulating an integrated circuit which includes a plurality of conductive nets that are electrically separate from each other, which includes a device having a plurality of conductive first sections that are each part of a respective net, and which includes a conductive second section external to the device, the second section being part of one of the nets which includes one of the first sections. A set of capacitances associated with the device is determined by: subdividing at least one of the nets on a theoretical basis so as to identify a plurality of net portions that collectively define the nets, in a manner so that the first and second sections are allocated to different net portions; treating the net portions as theoretically electrically separate from each other, while identifying respective capacitances between each net portion and each of the other net portions; and determining each capacitance of the set by summing the capacitances which have been identified between each of the net portions of one of the nets and a net portion of a further net. As to the net portions, it is possible for a given net portion to correspond to an entire net, or to only a portion of a net.